1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reading data regarding signature fuses through a normal read operation and a method of reading data regarding signature fuses in the semiconductor device through the normal read operation.
2. Description of the Related Art
The fabrication history of a semiconductor memory device can include useful information about the device and generally includes information regarding the mask, a fuse, wafer fabrication, package assembly, test results, and so on. Sometimes, critical fabrication history information is lost during manufacturing when the semiconductor memory device undergoes a wafer fabrication process, a package assembly process, and a module assembly process. Therefore, to prevent the loss of information, critical fabrication history is recorded within the semiconductor memory device.
Writing of the fabrication history can be performed on fuses included in the semiconductor memory device using a cutting process or a non-cutting process. Here, the fuses may be signature fuses that store data that specifies, for example, lot identification, the position of a die on a wafer, trimming fuses used to control AC timing and DC voltage/current, and redundancy fuses used to repair failed memory cells of the semiconductor memory device.
The fabrication history may be read from the semiconductor memory device using one of the following methods: (1) decapping semiconductor chips which are assembled together through a packaging process, and determining a pattern of cut/not cut signature fuses with the naked eye; (2) measuring currents flowing through an input pin, such as an address pin, which is coupled to a circuit via the signature fuses and reading data from the signature fuses in an analog manner; and (3) reading data from signature fuses in a test mode in a digital manner. A circuit with signature fuses from which data is read in the analog manner described in method (2) above is disclosed in U.S. Pat. No. 4,480,199.
FIG. 1 is a schematic block diagram illustrating the structure of a conventional semiconductor memory device 100 that is capable of reading data regarding the signature fuses in a test mode in a digital manner. Referring to FIG. 1, the semiconductor memory device 100 includes a fuse box selection circuit 110, a plurality of fuse boxes 121, 122, . . . , 12n, an output pipeline 130, an output control circuit 140, an output buffer 150, and a data input/output (I/O) pin DQ 160.
The semiconductor memory device 100 is, for example, an apparatus that satisfies the RLC specifications of a Rambus DRAM that can operate above a predetermined frequency, i.e., a high frequency, or satisfies the Input/output buffer information specifications of a synchronous DRAM that can operate at a high frequency.
The fuse box selection circuit 110 generates selection signals SELi (i is an integer from 1 to n) for respectively selecting the fuse boxes 121, 122, . . . , 12n, in response to a command signal CMD that is in phase with a clock signal CLK and a combination of address signals ADDR. The command signal CMD and the combination of the address signals ADDR may enable the semiconductor memory device 100 to enter a direct access (DA) mode and a signature fuse read mode, which are test modes, or to exit the signature fuse read mode. The signature fuse read mode is an operation mode where data is output from the signature fuses.
Each of the fuse boxes 121, 122, . . . , 12n includes a plurality of signature fuses and stores bit data regarding signature fuses, the data being at a logic high level (a level “1”) or a logic low level (a level “0”) depending on whether the signature fuses are cut or not. The fuse boxes 121, 122, . . . , 12n respectively output the stored bit data in response to the selection signals SELi. The output data may specify, for example, fabrication history information, related to the position of a semiconductor chip or a die on a wafer, a lot number, and a wafer number.
The output control circuit 140 generates a control signal for controlling the output pipeline 130 in response to the command signal CMD synchronized with the clock signal CLK. The command signal CMD may instruct the semiconductor memory device 100 to enter the signature fuse read mode.
The output pipeline 130 converts parallel data regarding the signature fuses, which is input from the fuse boxes 121, 121, . . . , 12n, respectively, into serial data SIG_D in response to the control signal generated by the output control circuit 140. Next, the output pipeline 130 sequentially outputs the serial data to be in phase with the clock signal CLK.
The output buffer 150 selects one of the serial data SIG_D output from the output pipeline 130 and output data DOUT generated during a normal read operation, in response to a command signal CMD that is in phase with the clock signal CLK and a combination of address signals ADDR. Then, the output buffer 150 sends the selected data to the data IO pin DQ 160. The command signal CMD and the combination of the address signals ADDR may enable the semiconductor memory device 100 to enter the signature fuse read mode that is a test mode, or to perform the normal read operation. During the normal read operation, the data DOUT is read from memory cells (not shown) of the semiconductor memory device 100.
FIGS. 2A and 2B are illustrative timing diagrams of a read operation involving the reading of signature fuse data for the semiconductor memory device 100 of FIG. 1. More specifically, the timing diagrams shown in FIGS. 2A and 2B refer to a read operation for reading data regarding the signature fuses in a Rambus DRAM.
Referring to FIGS. 2A and 2B, the read operation is performed in the following sequence of steps: direct access mode setting, signature fuse read mode setting, register framing, request packet inputting, address packet inputting, dummy packet outputting, and signature fuse data reading.
During the direct access mode setting, a direct access (DA) mode, which is a test mode, is set in response to a command signal CMD, which is in phase with a clock signal SCK, and a combination of address signals ADDR input from a serial I/O pin SIOφ. Then, a direct access mode signal DAmode that indicates activation or inactivation of the DA mode, is activated to a high level.
During the signature fuse read mode setting, the signature fuse read mode which is a test mode, is set in response to a command signal CMD which is in phase with a clock signal SCK and a combination of the address signals ADDR input from the serial I/O pin SIOφ. Then, a signature fuse read mode signal SIG_RD that indicates activation or inactivation of the signature fuse read mode, is activated to a high level.
During register framing, a starting point of an input packet is determined. Next, during the request packet inputting step, a request packet is input via the serial I/O pin SIOφ, the request packet instructing a read operation of a control register in the Rambus DRAM. Next, during the address packet inputting section, an address packet, which is used to select one of the fuse boxes 121, 122, . . . , 12n of FIG. 1, is input via the serial I/O pin SIOφ. Thereafter, during the dummy packet outputting and the signature fuse data reading sections, a dummy packet is output via the serial I/O pin SIOφ, and then, signature fuse data SIG_D is read. FIG. 2B illustrates outputting of 16-bit signature fuse data F1, . . . , F16 in synchronization with the clock signal SCK.
However, since the conventional semiconductor memory device 100 reads the signature fuse data directly through a data read path, circuits, such as the fuse box selection circuit 110, the fuse boxes 121, . . . , 12n, the output control circuit 140, and the output pipeline 130, which output the signature fuse data are connected to the output buffer 150, thereby increasing the load placed on the output buffer 150. In view of the increased load on the output buffer due to the signature fuse test circuitry, the read speed of the output data DOUT output via the output buffer 150 may become slow during a normal read operation.